
module clk_lcd(
   input       clk_in,
   input [7:0] signal_open,
   output      LCD1_CLK_P,
	input 		Display_Mode,
	input 		MCU_RD
);
   
   reg         clk_o;
   
   always @(*)
		if(~Display_Mode)
		begin
			if (signal_open == 8'h01)
				clk_o = ~clk_in;
			else
				clk_o = 1'b0;
		end
		else if(Display_Mode)
		begin
			clk_o = MCU_RD;
		end
   assign LCD1_CLK_P = clk_o;
   
endmodule
